Avula H. - ASIC DV Engineer

Avula H.

ASIC DV Engineer

United States | America/Adak (USD)

$1/hr
Part-time:10-30 hrs/week
0, Followers

ABOUT ME

Industry Experience: Good understanding of Computer Architecture concepts Good understanding of Verilog, SystemVerilog, SV Assertions, UVM, On-Chip protocols, Memories[CCMs, Caches, DDR]. Good experience with Digilent ZyBo Z7-10, Synopsys HAPS FPGA prototype and ZeBu emulation platform. Technical Skills: HDL : Verilog HVL : SystemVerilog TB Methodology : UVM HDVL Tools : AMDs Xilinx Vivado, Synopsys VCS, Cadence Xcelium, Siemens Modelsim. FPGAs/Emulators : Digilent Zybo Z7-10, Synopsys HAPS-70/80, Synopsys ZeBu. Editors : gedit, Gvim, LaTex Scripting : Perl Version Control : Perforce Programming Languages : C, Python Running simulations using Makefile Research/Educational/Industry Interests: Computer Architecture Digital Logic Design CPU/RTL/ASIC/SOC Design CPU/RTL/ASIC/SOC Design Verification Hardware Verification/Validation Industry Projects worked on: Worked 4 years as CPU Functional testing engineer for Synopsys ARC Processor Team Hands on experience with Synopsys HAPS FPGA and Synopsys ZeBu emulator for validating ARC Processor Personal Projects worked on: RTL Design, Synthesis and Verification of 5-stage 32-bit MIPS Pipelined Processor Router 1x3 - RTL Design and Verification Verification of Hyper Transport Advanced X-bar(HTAX) Protocol AXI UVC - AMBA AXI4 Protocol Verification AMBA AHB2APB Bridge design UART-IP Core Verification SPI Master Core Verification Educational Projects worked on: Health Monitoring System Design Air Quality Monitoring System Design Automated Vehicle Parking Lot system Design Automatic Library Management System Design using RFID Smart water Distribution System Design Wi-Fi controlled Robot Design 8051 Development Board Design

SKILLS