Amit

ABOUT ME

 Expertise in Developing UVM/System Verilog based testbench from scratch
 Skilled at Developing Testplan, Testcase, Track and Debug bugs in Design
 Expertise in writing and analysis of Coverage and Assertion in System Verilog
 Experience in IP blocks implementation(RTL Design) using VHDL and Verilog
 Experience in Ultra Low Power & Generic Design Development
 Experience in Developing of Design Specification, Micro Architecture & Integration Guide
 Communication IP’s protocol like SPI, I2C, USB2.0,USB 3.0 and BLE Controller, Ethernet Switch.
 Good Experience of AXI3 & Wishbone SoC Bus
 Good Design Experience of IP’s like GFSK Modem, CRC16, RAM Controller, SPI, I2C,USB2.0
 Strong understanding of digital design

SKILLS