Fasahat H.

ABOUT ME

I have been working in a FPGA outsourced job company for the last 12 years with experience in RTL design in FPGA(s) from Stratix II all the way to the latest Stratix 10, Agilex FPGA chips. Similarly, I have experience in RTL design, synthesis and timing closure on Xilinx platform(s) such as Ultrascale, Ultrascale+ and 7-series. In addition, I have been implementing DSP chain and error control coding cores on FPGA.

SKILLS